Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs

Abstract. Different to common approaches we propose a novel Finite State Machine (FSM) partitioning procedure which takes technology-specific features into consideration. Moreover, partitioning and state encoding are performed simultaneously. We discuss the method utilizing the technology of Lookup-Table (LUT)-based FPGAs in detail. Our implementation can be used as an add-on for usual FPGA synthesis systems. We inserted this procedure into the FPGA design flow and achieved average area reductions by 38% and saved circuit depth by 29% for large FSM benchmarks.